A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration

In this paper, an efficient method to achieve defect-tolerance with embedded single-port word-oriented RAM is presented. The defect tolerance of the RAM is based on a hierarchical redundancy technique employing a self-test and self-reconfiguration logic and is applicable to any standard RAM device. The presented approach is based on a two-level redundancy. Therefore, the memory is split in b smaller RAM blocks of equal size plus one redundant block. Each of those b+1 blocks is equipped with four spare rows and contains a simple self-test logic to detect and mask defects on the lower redundancy level by replacing defective rows. In the last phase of the procedure, b reconfigured (or defect-free) blocks form the RAM on the higher level. This redundancy technique leads to a significant increase in yield with a comparatively low area overhead. Furthermore, only a very moderate delay in the signal path is added so that there is nearly no decrease in the memory's performance. A 1 MBit DRAM-organized as 32 k/spl middot/32 Bit-with an interleave access mode for high performance data rates was designed.