Calibration of library element optimization to improve static power

Library elements (or standard cells) are basic building blocks of integrated circuits. These are built early in the technology cycle. Small changes to library elements can result in significant power/performance changes to large designs instantiating them. Qualifying these small changes on silicon can benefit products. Several physical layout optimizations are performed to improve performance and/or reduce standby power. This paper demonstrates the application of ring oscillators to calibrate such optimizations. These ring oscillators are designed to provide cell-specific validation and feedback to the entire library optimization. Silicon calibration results from 55nm technology node are discussed.