Architectural design of a highly programmable Radix-2 FFT processor with efficient addressing logic

A large number of efficient fixed geometry Fast Fourier Transform (FFT) VLSI designs have been developed till date. We propose a novel architectural design for a highly programmable Radix-2 Decimation-In-Frequency (DIF) FFT processor using relatively simple memory addressing logic. The 5-level programmability of the design, allows computation of 64, 128, 256, 512 or 1024 point FFT of the input signal, depending on application. Besides, the architecture provides the flexibility of computing an N point FFT for M length data (N > M), i.e. with an enhanced resolution also. A complete system flow of the entire FFT architecture along with twiddle factor multiplication, bit reversal and a detailed efficient Address Generation Block (AGB) are also presented. The address generation methodology adopted for the proposed design is based on counters and multiplexers which significantly saves the hardware as well as the latency requirement introduced thereon.