A 5-GS/s 4-bit flash ADC with triode-load bias voltage trimming offset calibration in 65-nm CMOS

A 5-GS/s 4-bit flash ADC is implemented in 65-nm CMOS. Offset calibration is achieved by digitally adjusting the bias voltages of the triode loads in the preamplifier without introducing additional capacitive loading in the analog path and degrading the high-speed performance. The ADC consumes 34.3 mW from a 1.2-V supply at 5 GS/s, and occupies 0.0828mm
²
active area. The ADC achieves 3.93 ENOB with a 2.5-GHz ERBW and a 0.45-pJ/convstep FOM at 5 GS/s.