Low-Voltage Oxide-Based Electric-Double-Layer TFTs Gated by Stacked $\hbox{SiO}_{2}$ Electrolyte/Chitosan Hybrid Dielectrics

Low-voltage oxide-based electric-double-layer (EDL) thin-film transistors (TFTs) gated by stacked SiO
₂
electrolyte/chitosan proton-conductor hybrid dielectric have been fabricated on glass substrates at room temperature. Such EDL TFTs exhibit a saturation mobility (μ
_sat
) of 7.8 cm
²
V
^-1
s
^-1
, a subthreshold swing (S) of 100 mV/decade, a drain current on/off ratio (I
_on/off
) of 7.8 × 10
⁵
, and a threshold voltage (V
_th
) of -0.48 V. After aging for one month in air ambient without surface passivation, such device shows μ
_sat
of 3.5 cm
²
V
^-1
s
^-1
, I
_on/off
of 1.2 × 10
⁵
, and S of 120 mV/decade. Control experiments demonstrate that devices gated by stacked SiO
₂
electrolyte/chitosan hybrid dielectrics show improved stability compared with TFTs gated by single chitosan or single SiO
₂
electrolyte gate dielectric.