Underfill characterization for multi-layer 3D-SiP stacked chip package

In this paper, evaluation of underfill materials for 3D SiP packages where micro bump interconnections and solder bumps has been presented. Characterization of underfill materials was carried out in terms of adhesion testing on various chip passivation surfaces and process optimization for void free filling. Capillary underfill materials have been evaluated for micro bump interconnections for 3D stacked module with different size chips as well as 3D stacked module with same size chips, and moldable underfill has been evaluated for over molding of stacked module along with underfilling of solder bump interconnections. Die shear test was carried out on adhesion test samples and results revealed failure between chip and polyimide layers in polyimide samples, and mixed failure between underfill and passivation layer in SiN samples. Process optimization for void free underfilling for CUFs were carried out based on dispensing temperature, speed, length, pattern and effects of plasma treatments. For MUF, the transfer molding process optimization was carried out by varying transfer time and die temperature to achieve void free underfilling and molding process. CSAM and through scan analysis was carried out on the under filled samples to check the quality of the underfilling process. The optimized process results shown void free underfilling for both 3D stacked module packages with different size chips as well as same size chips.