Power distribution fidelity of wirebond compared to flip chip devices in grid array packages

We have simulated the power fidelity of wirebond and flip chip grid array packages suitable for next generation microprocessors. The dc power droop across the chip from resistive losses and the ac power noise from switching events were studied as a function of the number of package power planes, dielectric constant, the number of chip connections, decoupling capacitors, and their location. Simulation program with integrated circuit emphasis (SPICE) was used to simulate the effects of the package and printed wiring board (PWB) characteristics on the differential power supply noise. We varied the number of package power planes, their dielectric constant, and the use of discrete decoupling capacitors and capacitor location with a goal of finding the best low cost design for effective power delivery to the chip.