Accelerating the artificial bee colony algorithm by hardware parallel implementations

Artificial bee colony (ABC) is an optimization algorithm inspired on the intelligent behavior of honey bee swarms. It is suitable to be applied when mathematical techniques are impractical or provide suboptimal solutions. As a population-based algorithm, the ABC suffers on large execution times specifically for embedded optimization problems with computational limitations. For that we propose a hardware parallel architecture of the opposition-based ABC algorithm (HPOABC) that facilitates the implementation in Field Programmable Gate Arrays (FPGAs). Numerical simulations using four well-known benchmark problems demonstrate that the opposition-based approach allows the algorithm to improve its functionality, preserving the swarm diversity. Additionally, synthesis results point outs that the HPOABC architecture is effectively mapped in hardware and is suitable for embedded applications.