Effects of single-electron transistor parameter variations on hybrid circuit design

A behavioral model for the single-electron transistor (SET) that includes variations for the tunneling resistance is introduced. The resulting model is recast in a closed analytical form that expresses the characteristics of the single-electron transistor and it is implemented in a Verilog-A module to be used in hybrid simulation of MOS-SET circuits. Model generation has been achieved by using a piecewise linear techniques.