An efficient hardware architecture of the H.264/AVC Half and Quarter-Pixel Motion Estimation for real-time High-Definition Video streams

The H.264/AVC is the newest digital video compression standard developed by the Joint Video Team (JVT). This standard includes new algorithms as the Fractional Motion Estimation that enhances the coding efficiency and compression rate of video sequences implicating a higher computational complexity. The H.264/AVC is most commonly used for High Definition Video (HDTV) real-time broadcasting for Digital Television, demanding hardware implementations of the CODECs. In this work, an efficient hardware architecture for the Half and Quarter-Pixel Motion Estimation is proposed. The design was described using VHDL and synthesized to the ALTERA Cyclone II FPGA being able to process real time HDTV (1920×1080) video streams (30 frames per second). The synthesis results establish a maximum frequency of 105.22 MHz after applying optimization methods, being able to process 41.62 HDTV frames per second (fps).