A stoppable four-phase clock generator for low-power and low-noise applications

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for low-power and low-noise on-chip devices. The device is constructed around a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm
²
. With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.