A new pipelined network interface for Network on Chip with latency and jitter optimization

To facilitate the use of the NoC techniques an efficient design of the network interface (NI) unit that connects the switched network to the IP cores is required. In this paper, we present a new pipelined NI architecture for NoC. We introduce a new distributed buffer structure that increases area and reduces latency and jitter. The low latency and minimal jitter between packets are obtained through the separation between header and payload memories. The modular design is obtained through the separations between injection and extraction path and between IP and network sides. The latter separation allows IPs and NoC to be designed independently from each other. For evaluating the efficiency of this approach, we use AHB standard at the IP side and we use the most three used flow controls in NoC. A performance study was conducted and NI designs were synthesized with ST 0.13μm CMOS technology using High speed library. Experimental results show that the proposed NIs allow better results in terms of latency, area and dissipated power relatively to the current published state-of-the art NI architectures.