A design methodology of bipolar standard cell LSIs for Gbit/s signal processing

A bipolar standard cell LSI design methodology for Gbit/s LSIs is described. A unique configuration of cell libraries which have internal fixed routing channels especially for differential clocks and a clock distribution scheme that considers the equal length and load of differential clocks makes it possible to achieve a 1.8 Gbit/s 2.5 K-gate LSI.