Delay models for timing simulation of CMOS/BiCMOS/BiNMOS mixed digital circuits

The authors report on delay models for three basic structures, CMOS, BiCMOS and BiNMOS inverters. The models account for input slope. They also account for the various second order effects such as short channel effects in MOS transistors, high current effects in BJTs, and the device parasitics of MOS and BJT transistors. The error between the delay models and SPICE is for most cases within 5%. The models have been implemented within a simulator used to estimate the propagation delay of a chain of mixed CMOS/BiCMOS/BiNMOS inverters. The error between the delays estimated by the simulator is two orders of magnitude faster than SPICE.