Tutorial T7B: Optimally Addressing Verification Constraint Complexity for Effective Functional Convergence

As SoC design becomes larger and more complex, verification engineers are expanding constrained-random testing to meet the validation demand. This expansion creates a new set of challenges: engineers now face exponentially growing verification performance and capacity issues. It is no longer enough to write constraints that simply function to validate a design. Today, engineers must also optimize the constraints they write for performance if they wish to have any hope of both successfully validating their design and meeting their deadlines. In this tutorial, we discuss a scalable methodology for writing constraints and optimizing performance is which will improve engineers' productivity to write and debug ever-increasing amounts of larger, more complex sets of constraints. Our goal is to reduce the time needed for functional convergence, and later for debug and volume manufacturing. We will also discuss the vital role of Verification IP providers and users in this scenario.