An effective level-1 cache locking strategy for energy-efficient real-time multicore systems

Multicore architectures with multilevel caches are being used in both desktop and embedded processors for their improved performance. Caches increase execution time unpredictability and make it difficult to support real-time applications. Caches also challenge the power supply system by consuming a lot of power. Studies show that cache locking improves predictability and performance/power ratio for single-core systems. Recent studies also show that way cache locking can be applied in multicore systems. In this work, we propose a simple but effective level-1 way cache locking scheme for multicore systems. This scheme is based on the analysis of applications' worst case execution time (WCET) and it allows changing the locked cache size during runtime to achieve the optimal predictability and performance/power ratio for the running application. Using Heptane WCET analyzer, we study MPEG4, H.264/AVC, FFT, MI, and DFT codes and generate workloads. Workloads provide miss information for the memory blocks (without cache locking). Using VisualSim tool, we model and simulate a system with four cores and two levels of caches. We also simulate a random cache locking strategy. Experimental results show that our cache locking scheme significantly improves predictability by decreasing total misses more than 50%. Experimental results also show that our proposed cache locking strategy outperforms the random strategy by up to 22%.