Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOS

This paper presents a two-stage modulator for low noise and low power design. The modulator is driven by LO and 2LO; by rejecting noise from the LO path, the modulator achieves a noise floor of -161dBc/Hz at an offset frequency of 40MHz. The modulator also enables the use of a low power injection locked frequency divider (ILFD) to generate quadrature LO. Supplied by 1.2V, the whole circuit consumes only 7.6mA. The modulator is designed in a 65nm CMOS process.