Design of a high performance and low power 1Kb 6T SRAM using bank partitioning method

This paper deals with the design and analysis of 1Kb Static Random Access Memory (SRAM) at 180nm, focusing on optimizing power and delay. The entire SRAM can be divided into 4 blocks with each block having equal capacity of 256b. The key of low power operation in the SRAM is to reduce the wordline capacitance. The sense amplifier is placed below the column decoder circuit. Here only one sense amplifier is used as size of the memory is not large. To reduce power we have used memory bank. Memory bank is selected using block selector circuit. The power dissipation is less in the circuit containing memory bank because in memory bank wordline capacitance are reduced as only one bank is selected at a time and all the other remain in standby mode. Here sense amplifier, bit line conditioning circuit and decoder are also designed and verify various results. All the simulations are performed using IC flow tools at TSMC 180nm technology.