FPGA architecture for object extraction in Wireless Multimedia Sensor Network

This paper presents the architecture of a FPGA-based efficient image processing system suited to Wireless Multimedia Sensor Networks. The system consists of two major processing elements: a customized processor for the networking functions and an image processing block. The latter enables the system to detect and extract any updated objects in captured images in real-time. The proposed architecture is optimized to achieve high speed processing with minimum hardware requirement and power consumption. Experimental results show that for a detected object of average size, the proposed architecture helps to reduce the total energy consumption by approximately twenty times compared to the energy consumed for raw image transmission. The system was successfully designed and implemented on FPGA. Implementation results of a network utilizing the proposed architecture reveal that this novel approach is suitable for Wireless Multimedia Sensor Network due to low hardware and low energy requirement for image communication.