A study on accelerated built-in self test of multi-Gb/s high speed interfaces

An efficient built-in self test (BIST) method is proposed for accelerated bit error rate (BER) test. The BIST can intentionally generate timing and voltage offsets at the data transmitter in order to measure the timing and voltage margins by drawing stereographic BER diagram on a voltage-time plane. Linear numerical models for `BER vs. time' and `BER vs. voltage' are established and verified by the measurement results from various sources. The acceleration test sequence based on the linear model completes the BER test down to 10
^-15
level in 150msec.