Design and FPGA implementation of a QoS router for Networks-on-Chip

Network-on-Chip (NoC) is believed to be a solution to the existing and future interconnection problems in highly complex chips. Different alternatives proposed circuit-switched NoCs to guarantee performance and Quality-of-Service (QoS) parameters for Systems-on-Chips (SoC). However, implementing scheduling mechanisms with different service classes and exploring the advantages of wormhole routing and virtual channels is an important way to provide QoS guarantees in terms of transmission delays and bandwidth. This paper presents a packet-switched NoC router with QoS support. It uses a priority-based scheduler to solve conflicts between multiple connections with heterogeneous traffic flows and to minimize network latency. The hardware design of the router has been implemented at the RTL level; its functionality is evaluated and QoS requirements for each service class are derived. We show the trade-off between an optimal scheduling strategies implementation and the performance of the system.