Analysis of SRAM hierarchical bitlines for optimal performance and variation tolerance

Hierarchical bitlines improve performance and power consumption due to the reduced bitline capacitance associated with read/write operations. This paper analyzes hierarchical bitlines and provides optimal solutions for maximum performance and minimum variance. Simulation results demonstrate that the optimized 2-stage hierarchical bitlines in the conventional 6T and 8T SRAMs improve the performance by 41.5% and 63.8%, and the performance variance (σ
²
) by 65.7% and 88.0%.