Analytical modeling and simulation for dual metal symmetrical gate stack (DMGAS) cylindrical/surrounded gate MOSFET

The advancement of CMOS technology has enabled the Si based industry to meet the technological requirements according to the market needs. Rapid advancement and steady downscaling of device dimensions establish these requirements. Miniaturization of MOSFET leads to short channel effects (SCE) and a reduction in current drivability. Various architectures are proposed to overcome the scaling limitations. Among this cylindrical /surrounded (CGT/SGT) gate MOSFET offers a high packing density, steep subthreshold characteristics and higher current drive. This structure has a large effective channel and the gate surrounds the silicon pillar results in high packing density and increased SCE immunity.