Wideband receiver for Software Defined Radio in GHz range using standard 40nm CMOS technology

In this paper, a low power wideband receiver for Software-Defined Radio (SDR) is presented. In SDR design, the receiver should be able to receive signals over a broad-bandwidth so that a variety of different communication standards can be covered. In the proposed design, a 0.1–6 GHz analog front-end for SDR is demonstrated. Implemented in a standard 40nm CMOS technology, the proposed receiver is realized without inductors and able to work between 0.1–6 GHz while consuming less than 4.55mA current from a single 1.1-V supply voltage.