Adaptive spread spectrum clock tracking for interpolator-based clock and data recovery

A 3Gb/s half-rate interpolator-based clock and data recovery (i-CDR) with asynchronous spread spectrum clock (SSC) tracking capability is presented. The i-CDR comprises a proportional path to track phase error and an integral path to compensate frequency offset. The integral path consists of ppm detector and ppm decoder with a combiner acts as the integration point between the two paths. The ppm decoder exploits averaging algorithm to facilitate wide range ppm tracking for triangular modulation profiles. The i-CDR, implemented in TSMC 60nm LP 1P11M CMOS technology occupies an active area of 390μm × 800μm and consumes 48.8mA from a 1.2V power supply when operated at 3Gb/s. Silicon measurements substantiate that the i-CDR has ppm tolerance up to +/-5000ppm.