Program-aware circuit level timing analysis

There is an increasing need for accurate timing information in nanoscale CMOS integrated circuit design. As delay variability increases design margins tend to be overly pessimistic in worst case circuit design. Conventional timing characterization methods do not take the function of the circuit into account. The use of program information tightens the result of circuit level timing analysis and reduces overestimation of worst case circuit delay. The method presented in this paper is able to analyze the impact of program specific details on the delay in the presence of process variations. Additionally we show how the gained information can be used to analyze different instruction sequences towards robustness in a microprocessor.