Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si
₄₅
Ge
₅₅
/Si cap deposition and the workfunction metal, high performance devices with balanced V
_t,sat
(+0.12V, -0.16V) at scaled T
_inv
~1nm and gate length L
_g
~30nm are reported, leading to 17ps ring oscillators at 1μW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.