Cycle-accurate configuration layer model for Xilinx Virtex FPGAs

A cycle-accurate VHDL simulation model for the Xilinx Virtex-4 (and on) FPGA Configuration Layer is presented. This model allows for simulating configuration memory SEU injection and correction dynamics, as well as control logic SEFI recovery, with independence from Application Layer. Scrubber designs can be efficiently simulated, together with one or more instances of this model, prior to hardware implementation. This significantly improves design observability and simplifies the validation of such designs.