A technique to improve the performance of fixed-point TDMP decoding of QC-LDPC codes in the presence of SNR estimation error

Most high-throughput, fixed-point processors offer at least two options for arithmetic operations: 8-bit arithmetic, and 16-bit arithmetic. The lower resolution provides higher computational throughput at the cost of poorer performance in many applications. We investigate the effect of the resolution of saturating, fixed-point arithmetic on the performance of the turbo-decoding message-passing algorithm with quasi-cyclic low-density parity-check codes. We consider limits on the magnitude of extrinsic updates as a means to mitigate the effect of posterior-value saturation on the decoder's performance. We show that a fixed limit on updates only partially overcomes the greater effect of saturation in 8-bit operations, whereas a limit that depends on the degree of the variable node results in performance almost as good as what is possible with 16-bit operations.