Using synthesis, simulation, and hardware emulation to prototype a pipelined RISC computer system

This paper describes a VHDL based rapid prototyping approach to simulate, synthesize, and implement a prototype computer system using commercial CAD tools, a meta assembler, a retargetable C compiler, and FPGAs in a hardware emulator. This methodology is utilized in a senior design laboratory sequence of two required courses for computer engineering students at Georgia Tech.