A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits

This paper presents a 900 Mbps capacitive I/O link for wireless wafer-level testing of integrated circuits (ICs). Pulse width modulation (PWM) is adopted to embed clock information into data signals to implement single-channel communication. PWM signals are demodulated by a delay-locked loop (DLL) based bit-slicer utilizing a 1-cycle locking phase detector (PD). DC level-shifting due to DC-unbalanced symbols is mitigated with a feed-forward clock selector. An I/O prototype, fabricated in 0.13 μm CMOS achieves a bit-error-rate (BER) less than 10
^-13
at 900 Mbps. The total area of both the transmitter and receiver is less than the silicon area of a conventional standard I/O cell.