Optimization of placement of dynamic network-on-chip cores using simulated annealing

We derive an objective function which instead of mapping/placing application task graphs in a compact manner onto reconfigurable devices, dilates the mappings as much as the available latencies on critical connections allow. The objective function is then optimized using simulated annealing. The main advantage of the dilated placement of the task graphs is that the unused resources between an application's configured components can be used to provide additional flexibility when the configuration needs to change. We present results of applying the dilated placement to one synthetic case and one real case. The presented results show successful and meaningful graph dilation.