A bit-level pipelined VLSI architecture for the running order algorithm

A bit-level pipelined VLSI architecture for the running order algorithm is presented. Based on the proposed modified algorithm, the deletion and the insertion is successfully pipelined in the bit-level operation. A block processing architecture of this modified algorithm is also constructed. The pipelined cycle of the proposed architecture is merely equivalent to the delay time of a pair of 1-bit comparisons that is independent on the window size and the signal resolution.