A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance

This paper presents a system-on-a-chip for fault detection and fault-distance-estimation for power transmission lines in the smart grid. Toward this goal we have designed and fabricated three chips: PGS4, PGS5 and PGS6, each successively more advanced than the previous one. PGS4 and PGS5 each have two spiral sensors, of which one is dedicated to sensing the transmission line current, and the other serves as a redundant sensor (in case of defects on the primary one), but also as a transmission line emulator in the test phase. In this latter role, i.e., as driver, a new model for the coupled coils is proposed. These chips seek to implement an advanced fault distance estimation algorithm proposed by Radojevic which utilizes frequency domain measurements of the transmission line voltages and currents. Specifically, the fault distance is estimated using the Fourier coefficients of the fundamental and third harmonic in an algebraic formula. PGS5 and PGS6 are able to perform this analysis, with some differences as delineated in the paper. The sensor spiral feeds into a high gain amplifier and a source follower, termed as the frontend, which is the key to the operation of the chip. Therefore three copies, actually variations, of the frontend, selectable with a multiplexer, are provided for defect tolerance. For the Fourier analysis needed for fault distance estimation, we have used a powerful digital macro, MA_PLUS, which has been presented in our previous papers. We have successfully tested PGS4, and some test results are included for PGS5. Test results for PGS6 will be presented at the conference. As stated earlier, these designs are successively more advanced with a view toward enhancing the probability of success of the final design. Results for defect tolerance for the coils and the frontends are included in the paper.