Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis

Post-silicon debugging process is aimed at locating errors not detected during the process of pre-silicon verification. Although in the post-silicon validation engineers can exploit the high speed of hardware prototype to exercise huge amount of test vectors, low level of real-time observability and controllability of signals inside the prototype is a big issue. Various Design for Debug (DFD) techniques aim to improve the observability of signals and expedite the root cause analysis of errors. Typical practical DFD approaches are based on the Embedded Logic Analysis (ELA), using a trigger unit that can effectively control when to acquire the debug data. In this paper, we propose a hierarchical trigger generator that builds a trigger unit. Additionally, it provides resourceful and compact trace information for root cause analysis. Major advantages over traditional trigger units are: 1) by keeping the trace of interactions that leads to the failure, it facilitates the process of failure localization and root-cause analysis 2) it can be tuned for the specific location of a design to avoid the huge cost related to interfacing with trace signals 3) it can get parameterized to generate several units that can be placed inside the limited area in multiple debug rounds using a time-multiplex fashion.