Mechanisms of Threshold Voltage Shift in Polymorphous and Microcrystalline Silicon Bottom Gate Thin-Film Transistors

In this paper, we have studied the stability of polymorphous silicon (pm-Si:H) and
$\mu{\hbox{c-Si:}}{\hbox {F:}}{\hbox{H}}$
bottom gate thin-film transistors (TFTs) by combining degradation and relaxation experiments under various stress conditions. We report on polymorphous silicon (pm-Si:H) TFTs with
$\Delta V_{\rm TH}=1\ {\hbox{V}}$
after 10 h of stress and
$\mu{\hbox{c-Si:}}{\hbox {F:}}{\hbox{H}}$
TFTs with superior stability, which show a
$\Delta V_{\rm TH}$
of only 0.05 V under stress conditions similar to those encountered in active-matrix operation regime (
$V_{G}=12\ {\hbox{V}}$
and
$V_{D}=10\ {\hbox{V}}$
). Relaxation studies show that the quality of the interface between silicon nitride and pm-Si:H (or
$\mu{\hbox{c-Si:}}{\hbox {F:}}{\hbox{H}}$
) controls the stability at short stress times. Interestingly, the deposition conditions of the semiconductor layer seem to modify the quality of the a-SiN:H and thus the stability of the interface.