A variable gain distributed amplifier with low voltage and low power in 0.18-μm CMOS technology

In this paper, a variable gain distributed amplifier (VGDA) is demonstrated using 0.18-μm CMOS technology. The forward body bias and the variable-resistance PMOS are utilized to achieve a low voltage and low power VGDA. The VGDA presents a measured maximum small signal gain of 18.1 dB, a 3-dB bandwidth from 2.2 to 13.6 GHz, and a gain control range of 38 dB. The noise figure is between 4.9 and 5.6 dB from 3.1 to 10.6 GHz. The highest-bias is 0.7-V and the power consumption is 25 mW under 0.62-V gate bias. The chip size is only 0.58 mm
²
. To author's knowledge, this circuit has the lowest power consumption and smallest chip size among all the reported variable gain distributed amplifiers covering 3.1 to 10.6 GHz.