High-performance FPGA implementation of packet reordering for multiple TCP connections

This paper presents an FPGA-based design and implementation of TCP packet reordering for multiple TCP connections. In the packet processing, two FIFOs are used to preserve the packet header information and data information, respectively. The reordering process is based on the sequence and command information which can be used to determine where and how many to store the coming disorder packet or just send the ordered packet to application layer directly. This design has the advantages of high speed and good flexibility. The performance analysis shows that the data transmission collision is only 1.6% in the worst case. Using Altera FPGA, the design can be realized at 175 MHz working frequency.