Enhanced offset averaging technique for flash ADC design

This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC). The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μrn CMOS technology.