Impact of Well Structure on Single-Event Well Potential Modulation in Bulk CMOS

Perturbations in N-well potential have been shown to strongly affect the charge collection, charge sharing, and parasitic bipolar transistor characteristics. In this paper, temporal and spatial characteristics of the well-potential modulation are characterized through 3-D TCAD simulations. Effects of well-contact layout, ion energy, and technology process parameters for a 90-nm bulk CMOS process are investigated.