Performance evaluation of DIP policy on SMT processor system

Simultaneous Multithreading (SMT) processor got its high performance through fetching and executing multiple instructions from concurrent running threads with a shared hardware resources. Dynamic Insertion Policy (DIP) has been shown to have good performance for the cache. In this paper, we port the DIP replacement policy onto SMT processor based computer system, and evaluate the performance of it. The simulation experiments show that although some programs can obtain better performances with DIP policy in SMT processor the overall performance of the combined workloads are not so good as in a CMP processor based computer system.