A 1.5-V 3-mW 10-bit 50-Ms/s CMOS DAC with low distortion and low intermodulation in standard digital CMOS process

For telecommunication applications, the dynamic performance of a digital-to-analog converter such as intermodulation and spurious-free dynamic range is of the greatest importance and the static performance is of minor concern. This paper presents the design of a 1.5 V 10-bit CMOS digital-to-analog converter in a 0.6 /spl mu/m digital CMOS process for telecommunication applications. It features an intermodulation level less than -60 dBc at 10 Ms/s and -55 dBc at 50 Ms/s, and a spurious-free dynamic range of 59 dB at 10 Ms/s and 48 dB at 50 Ms/s. The power dissipation is about 1.5 mW at 10 Ms/s and about 3 mW at 50 Ms/s.