Mechanical and electronic analysis of 3D embedded capacitor filling with conductive adhesive

A three-dimensional (3D) PN junction capacitor for passive device integration (PDI) on silicon is discussed in this paper. The embedded capacitor with low parasitic inductor and high-reliability structure is a key technology for achieving effective micro-system integration for embedded passive technology and is widely used for a broad range of applications including filtering, tuning and power-bus decoupling in the substrate. Silicon Micro-Electron-Mechanical System (MEMS) processes and deep 3D pattern etching are used in the fabrication process followed by filling-in of the 3D capacitor structure by conductive adhesive, as will be discussed in this paper. The electrode design is designed to minimize parasitic inductance. The mechanical and thermal properties of the 3D as a function of capacitor trench depth and width are analyzed and optimized.