The fatigue failure analysis of 3D SiP with Through Silicon Via

Three-dimensional (3D) die stacking based on the Through Silicon Via (TSV) is a promising new packaging technology for its high performance, multi functionality, relatively smaller chip size and lower cost etc. However, the application of TSV in 3D SiP will introduce lots of new problems regarding the reliability, such as thermal stress, deformation, fatigue failure In this study, the thermal-mechanical reliability of a TSV-enabled 3D chip stack is simulated with FEA. Various design parameters are discussed regarding the system reliability: the number of stacked chips, the thickness of stacked chips, interposer, the diameter of TSV and the micro bump, the height of micro bump and the distance between the TSV.