3D packaging-combining chip on chip (COC) and chip on board (COB) packages-process and design considerations

In today's densely packed electronic circuit boards, 3D packaging of electronic components is commonplace. To further maximise use of real estate on PCBs or the substrate, 3D packaging of bare dies, wire bonded and encapsulated on substrates is becoming a necessity. Designers and manufacturers alike find constraints in width and length of substrates, but may have room in depth or height. The substrate layout is no longer restricted to area of space, but now volume as well. With the move to stacking bare dies, various issues in design and manufacture become critical. This paper investigates these issues, namely design considerations, process considerations and coefficients of thermal expansion of the end manufactured products. The average size of the products investigated ranges from a 6 mm/spl times/6 mm substrate to an 8 mm/spl times/8 mm substrate with a minimum of 20 aluminium wire bond interconnections.