Implementation of symbol timing synchronization for MB-OFDM UWB systems on FPGA

This paper proposes a design of symbol timing synchronization for MB-OFDM systems with low hardware consumption. Most of the existing algorithms for symbol timing synchronization cost a huge number of operations on cross-correlation or energy computing, so that, a great amount of multipliers and logic resources would be consumed if these algorithms are implemented on FPGA. The scheme proposed and implemented in this paper firstly locates the strongest muti-path by sign cross-correlation which has a low implementation complexity, and then finds the start of FFT window by utilizing an existing cross-correlation based algorithm inside a boundary, this boundary can be confirmed by the location of the strongest muti-path. The module for symbol timing synchronization has been designed in Quartus II, and the functional simulation result obtained shows correctness of the module.