Notice of Violation of IEEE Publication Principles: Model Based Comprehensive Functional Verification of RF SoC

Notice of Violation of IEEE Publication Principles

"Model based comprehensive functional verification of Rf SoC"
by YuHan Gao, LimTao Liu, RuZhang Li
in the 2011 Second International Conference on Digital Manufacturing and Automation (ICDMA), October 20, 2011, pp. 728-731.

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper contains significant portions of original text from the papers cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission.

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following articles:

"Modeling Approaches for Functional Verification of RF-SoCs: Limits and Future Requirements"
by Yifan Wang, Stefan Joeres, Ralf Wunderlich, Stefan Heinen Author Name
in the IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 28, No. 5, May 2009, pp. 769-773.

"Event Driven Analog Modeling for the Verification of PLL Frequency Synthesizers"
by Yifan Wang, Christoph Van-Meersbergen, Hans-Werner Groh, Stefan Heinen
in the 2009 Behavioral Modeling and Simulation Workshop (BMAS 2009), 2009, pp. 25-30.


Functional verification of RF SoC is a daunting task which results from its complexity in terms modes of operation, extensive digital calibration, and architectural algorithms. As what happened in digital circuit design, analog and RF (A/RF) verification has been becoming a separate and critical task from the recent on. In this paper, base-band modeLing and event-driven simulation technology are adopted to perform the functional verification of a RF SoC system which contains RF front-ends, mixer, IF filters, ADC/DAC, and the following digital data processing center unit. Mixed level co-simulation results of cadence AMS designer demonstrate the rationaLity of the proposed methodology.