An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of ${\rm V} _{\rm MIN}$ Degradation

Negative bias temperature instability (NBTI) has been considered as a main reliability issue in SRAMs since the threshold voltage degradation of PMOS transistors due to NBTI has raised minimum operating voltage (V
_MIN
) over time. This paper explains an SRAM reliability test macro designed in a 1.2 V, 65 nm CMOS process technology for statistical measurements of V
_MIN
degradation coming from NBTI. An automated test program efficiently collects statistical V
_MIN
data and reduces test time. The proposed test structure enables V
_MIN
degradation measurements for different SRAM failure modes such as the SNM-limited case and the access-time-limited case. The V
_MIN
dependency on initial device mismatch and stored data is also presented. The measured time to cell data flip affected by NBTI shows the similar trend of NBTI following a power-law dependency on stress time.