FPGA-Based Acceleration of Block Matching Motion Estimation Techniques

This paper focuses on the hardware acceleration of Block Matching motion estimation techniques (Search reduction family) suitable for the standard H.264/AVC MPEG-4 part 10 video compression. Many representative motion estimation search algorithms are explained here. As hardware, the well known Altera DE2 platform with a Cyclone II EP2C35F672C6 is used with a soft core NIOS II processor. C2H compiler which permits us to speed up the system at least two magnitude order is used to accelerate our source code. The paper shows the results in terms of performance and resources needed. This is the starting point to accelerate motion estimation algorithms using many strategies considering an ad-hoc motion estimation processor.