SyntHorus: Highly efficient automatic synthesis from PSL to HDL

We propose a linear complexity approach to achieve automatic synthesis of designs from temporal specifications. Each property is turned into a component combining monitor and generator features: the extended-generator. We connect them with specific components to obtain a design that is correct by construction. It shortens the design flow by removing implementation and functional verification steps. Our approach synthesizes circuits specified by hundreds of temporal properties in a few seconds. Complex examples (i.e. CONMAX-IP and GenBuf) show the efficiency of the approach.